Three generations on the same 3 nm family, seen from above. The interesting story is not core counts. It is where the matrix arithmetic moved, and then, at M5 Pro, the die splitting in two.
What you can see hereSwitch between four floorplans and select any block to read what it does and how it changed between M3, M4 and M5.
What this drawing is
Topology is real, geometry is illustrative
Block identities, core counts, process nodes and bandwidths are taken from Apple's own specifications and from the Counterpoint teardown of the M5 Pro. Block positions and relative sizes are schematic: they are arranged the way published die-shot annotations of M3 and M4 show Apple organising these SoCs, with the GPU array at one end, the CPU clusters and NPU adjacent, and cache and memory controllers along the perimeter. Nothing here is traced from a photograph, so read the topology as accurate and the geometry as illustrative.
Zoom · one GPU core
Where the matrix unit landed
M3 gave every GPU core a ray-tracing unit and a flexible on-chip memory pool. M4 sharpened both. M5 added something categorically different: a Neural Accelerator, a small FP16 and INT8 matrix engine, inside each of the ten cores. That is the whole "over four times the peak GPU compute for AI" claim, and it is why the M5's AI story lives in the GPU rather than in the Neural Engine.
One GPU core, three generations. The shader ALUs, the shared Dynamic Caching pool and the ray-tracing unit persist. M5 inserts a dedicated matrix-multiply block next to the ALUs, sharing the same core-local memory rather than sitting off on the Neural Engine across the fabric.
M5 Pro and M5 Max
One SoC, two dies
This is the real break with M3 and M4. The M5 Pro and M5 Max are not monolithic. Apple splits the SoC into a CPU die and a GPU and IO die, and bonds them with TSMC's SoIC-mH hybrid bonding; the marketing name is Fusion Architecture. Both dies are N3P, and Pro and Max ship the same CPU die, differing only in the GPU die.
The consequence worth staring at is this. The four LPDDR5X-9600 memory controllers live on the GPU die. So do the media engine and the display engines. Every CPU access to unified memory therefore crosses the bond interface. Hybrid bonding is what makes that affordable: direct copper-to-copper pads at a pitch fine enough that the inter-die hop costs a fraction of the energy an organic-substrate link would.
Package cross-section. The CPU die is bonded face-to-face onto the GPU and IO die, and only the lower die talks to the package substrate and therefore to the LPDDR5X stacks. The traced path is a CPU load missing in cache: it descends through the bond, is serviced by a memory controller that physically sits on the other die, and returns.
Structure per the Counterpoint Research teardown: TSMC SoIC-mH, N3P on both dies, unified memory maintained across the pair.
M3 → M4
Width, not layout
N3B to N3E, 25 billion to 28 billion transistors. Two extra efficiency cores, wider decode and better branch prediction on the performance cores, second-generation ray tracing, and a Neural Engine that roughly doubles to 38 TOPS. The floorplan is recognisably the same chip, grown.
M4 → M5
AI moves into the GPU
N3P, and identical core counts on paper. That is the point. The gain comes from ten new matrix engines inside the GPU cores, second-generation Dynamic Caching, and 153 GB/s of bandwidth to feed them. Metal 4's Tensor API is the software half of the same change.
M5 → M5 Pro and Max
The die splits
Monolithic becomes two hybrid-bonded dies. One CPU die serves both Pro and Max, while the GPU die carries 20 or 40 cores plus all four memory controllers. This is the reticle-and-yield escape hatch that lets Apple keep scaling the GPU without growing one enormous die.
Reference
The whole family, three generations
On the M5 Pro and Max core names: Apple and the teardown both describe the 18-core CPU as six Super Cores plus twelve Performance Cores on Armv9, not the familiar performance and efficiency split. Read literally, that is a renaming of the tiers, with what was a P-core becoming a Super Core and what was an E-core becoming a Performance Core. Apple has not said this outright, so treat the mapping as inference rather than fact. The base M5 of October 2025 still used the old wording: four performance and six efficiency cores.
Figures as published by Apple, except die areas (third-party measurement, marked est.) and the M5 transistor count, which Apple has not disclosed. Bandwidth is peak unified-memory bandwidth. Sources: apple.com/newsroom, M3 family 2023-10, M4 2024-05, M5 2025-10, M5 Pro and M5 Max 2026-03; Counterpoint Research, Apple M5 Pro chip teardown analysis.